The world is analog … or is it?
The Senior RF Analog IC Engineer will be responsible for block level design in Ku/Ka band RF Receivers & Transmitters for next generation of satellite communications in deep sub-micron technologies. You are responsible for architecture design, circuit design & verification, review for RFIC building blocks like PA, Phase Shifter, Active VGA.
You will develop new circuit architectures, design/verification methodologies to deliver ASICs that meet all the performance requirements in the required timeline. While the job primarily involves you to own block level designs, you will work closely with the layout engineer to ensure the layout meets all the constraints for the best silicon performance.
Ideal candidate will typically have 3 years of experience in the design of RFICs with at least one tape-out experience in deep sub-micron CMOS technology.
Location: Cambridge
Technical responsibilities
- Responsible for circuit design for RFIC building blocks.
- Delivering high quality RF/Analog blocks with leading edge performance using innovative architectures and circuit implementations with guidance from Senior design staff.
- Work closely with the layout team on IP floor-planning, trial layout design, parasitic extraction, and modifications.
- Document own work and actively participate in design reviews.
Organisational responsibilities
- Ongoing development of core competencies & technical skills
- Receptive and agile to the project needs.
- Good estimation of timescales for own tasks
- Follow good engineering practices including processes, documentation, tools & automation.
- Identify risks, flag issues in a timely manner so own milestones are achieved.
Essential qualifications and skills
- An Engineering degree in a relevant discipline
- Typically 3+ year experience in RFIC CMOS circuit design and processes (preferably 15GHz or higher operating frequencies) – including more than 1 successful tape-out.
- Cadence Virtuoso Design Framework Experience
- Ability to work, interact and collaborate within the ASIC team.
- Great communication skills and able to take responsibility for delivery of own designs to tight timescales.
Desirable
- Experience in 22nm FDSOI or other sub 45nm CMOS process nodes for RF/High speed ICs
- Experience with process relating to production release and qualification.
- Experience in EM modelling tools such as RFPro or EMX
- Experience in LNA design and RF PA
- Understanding of Radio systems, gain and noise budgeting, phase noise and intermodulation mechanisms
- Experience in RFIC Characterisation
- Experience in Chip ESD design & qualification
Cambridge Technology Centre:
Hanwha Phasor’s ASIC Centre of Excellence is based in Cambridge Science Park, comprising 150 acres/1.7 million square feet of high technology and laboratory buildings and home to some 7,000 people at over 130 companies, ranging from exciting start-ups to some of the world's leading technology businesses.
- Attractive landscaped setting, with abundant greenery, lakes and wildlife
- Gym, nursery, hairdressers, cafes, coffee shops and Cambridge’s famous foodPark, a collective of top-quality Cambridge-based street food traders – up to six food trucks arrive on site every Thursday, offering top-notch food year round, whatever the weather.
- Many cycleways and bus networks, linking to the rail network, which is a 10-minute walk away. Cambridge town centre is 10 minutes by car.
